This application claims the priority benefit of Taiwan application serial no. 090102583, filed Feb. 7, 2001.
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. Specifically, the present invention relates to a method of reducing the capacitance of a conductive layer and a semiconductor device obtained thereby.
2. Description of the Related Art
The increase in operational speed of a semiconductor device is an essential point in the development of the semiconductor industry and also is an important consideration for consumers when purchasing semiconductor devices. With the rapid development of the semiconductor circuit, the resistance of a conductive layer and the parasitic capacitance between the conductive layers have been critical factors among various factors that affect the operational speed.
Currently, a metal material having low resistance has been developed in order to reduce the resistance of the conductive layer. Improving the parasitic capacitance between conductive layers is achieved by using a material having a low dielectric constant instead of a conventional silicon dioxide as a dielectric layer between multi-layer metal connections.
However, the metal material and the dielectric layer having a low dielectric constant must be selected depending on the properties of the material and the process to be carried out. Therefore, the selection of the material is limited.
The present invention provides a method of reducing the capacitance of a conductive layer. The method is based on the existing process conditions, rather than selecting of a special material, to reduce the capacitance, of a conductive layer and increase the transmission speed.
That present invention provides a method of reducing the capacitance of a conductive layer, in which a well region is formed below and adjacent to an isolation and in a floating form.
According to one preferred embodiment, the above-mentioned method can be used in a process for fabricating a semiconductor device in which a conductive layer is formed a dielectric layer above an isolation. The above-mentioned method also can be used in a process for fabricating a semiconductor in which a local interconnection is formed on an isolation.
In the above-mentioned well region, the well region is a single well having a dopant type different than the doping type of the substrate. When the substrate has P type dopants, the well region has N type dopants; when the substrate has N type dopants, the well region has P type dopants.
A multi-well can be included in the well region. The multi-well comprises at least a first well region and a second well region, with the first well region being adjacent to the substrate and including the second well region therein, and the first well region having a different dopant type from the substrate and the second well region. When the dopant type of the substrate is P type, the dopant type of the well region is N type and that of the second well region is P type. When the dopant type of the substrate is N type, the dopant type of the well region is P type and that of the second well region is N type. floating well is not only formed below the isolation, but also adjacent to it. A depletion region can be formed at the interface between the floating well and the substrate. By connecting capacitance of the depletion region and the parasitic capacitance generated between the conductive layer and the floating well in series, the total parasitic capacitance of the conductive layer can be reduced so as to increase the operational speed of the device.